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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
FEATURES
* 6 differential LVHSTL outputs * Selectable crystal input interface or TEST_CLK input * TEST_CLK accepts the following input types: LVCMOS, LVTTL * Output frequency range: 15.625MHz to 500MHz * VCO range: 250MHz to 500MHz * Serial interface for programming feedback and output dividers * Supports SSC, -0.5% downspread. Can be enabled through use of the serial programming interface. * Output skew: 60ps (typical) * Cycle-to-cycle jitter: 30ps (typical) * 2.5V core/1.8V output supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8427-02 is a general purpose, six ICS LVHSTL output high frequency synthesizer and HiPerClockSTM a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8427-02 can support a very wide output frequency range of 15.625MHz to 500MHz. The device powers up at a default output frequency of 200MHz with a 16.6667MHz crystal interface, and the frequency can then be changed using the serial programming interface to change the M feedback divider and N output divider. Frequency steps as small as 125kHz can be achieved using a 16.6667MHz crystal an the output divider set for /16. The low jitter and frequency range of the ICS8427-02 make it an ideal clock generator for most clock tree applications.
BLOCK DIAGRAM
VCO_SEL XTAL_SEL TEST_CLK XTAL_IN OSC XTAL_OUT / 16 1 0
PIN ASSIGNMENT
VCO_SEL XTAL_IN nFOUT1 nFOUT0 FOUT1 FOUT0 VDDO VDD
32 31 30 29 28 27 26 25 VDDO FOUT2 nFOUT2 VDDO FOUT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TEST VDD FOUT4 nFOUT4 VDDO FOUT5 nFOUT5 GND
24 23 22
XTAL_OUT TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR
ICS8427-02
21 20 19 18 17
PLL
PHASE DETECTOR VCO /M /2 0 1
nFOUT3 / 1, / 2, / 4, / 8, / 16 OE GND FOUT0 nFOUT0 FOUT1 nFOUT1 FOUT2 nFOUT2 FOUT3 nFOUT3 FOUT4 nFOUT4 FOUT5 nFOUT5
MR
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
OE S_LOAD S_DATA S_CLOCK
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead VFQFN 5mm x 5mm x 0.75mm package body K Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8427DY-02 www.icst.com/products/hiperclocks.html REV. D JUNE 28, 2005
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16.6667MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6 NOTE 1.
The ICS8427-02 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16.6667MHz crystal, this provides a 1.0417MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 500MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The ICS8427-02 powers up by default to 200MHz output frequency, using a 16.6667MHz crystal (M = 192, N = 2). The output frequency can be changed after power-up by using the serial interface to program the M feedback divider and the N output divider. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16.6667MHz reference are defined as 120 M 240. The frequency out is defined as follows: fout = fVCO = fxtal x 2M N 16 N Serial operation occurs when S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N outputdivider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 (Power-up Default) 0 1 TEST Output LOW S_Data, Shift Register Input Output of M divider CMOS Fout
S_CLOCK
S_DATA
t
T1
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
SSC
t
S_LOAD
t
Time
S
FIGURE 1. SERIAL LOAD OPERATIONS
NOTE: Default Output Frequency, using a 16.6667MHz crystal on power-up = 200MHz (M = 192, N = 2) SSC off
8427DY-02
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
N DIVIDERS, SSC
AND
M
Test Mode Control Register
AND
TEST MODE CONTROL BITS
SSC Control Register
N Divider
M Divider
T1
T0 N2 N1
N0 M8 M7 M6 M5 M4 M3 M2 M1

M0 SSC

SSC
Data transfer from shift register to M and N dividers and SSC and Test Control Bits on a low-to-high transition of S_LOAD.
S_DATA
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
Shift Register
TEST Output T1:T0 = 01
8427-02 SHIFT REGISTER OPERATION - READ BACK CAPABILITY
1. Device powers up by default in Test Mode 01. The Test Output in this case is wired to the shift register. 2. Shift in serial data stream and latch into M, N, T1, T0 and SSC Control Bits. Shift in T1:T0=00, so that the TEST Output will be turned off after the bits are shifted in and latched.
TEST Output
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0 SSC
S_CLOCK
S_DATA
T1
t
S
T0
N2
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0 SSC
t
S_LOAD
H
Time
t
S
Data transferred to M, N dividers, TEST and SSC Control Bits. Changes to M, N, SSC and TEST mode bits take affect at this time.
Data latched into M, N Dividers, TEST and SSC control bits.
8427DY-02
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Type Power Output Output Input Power Output Power Output Output Pullup Description Output supply pins. Differential output for the synthesizer. LVHSTL interface levels. Differential output for the synthesizer. LVHSTL interface levels. Active High output enable. When HIGH, the outputs are enabled. When LOW, all 6 outputs drive differential low, FOUTx = Low, nFOUTx = High. LVCMOS/LVTTL interface levels. Power supply ground. Test output which is ACTIVE in the serial mode of operation. LVCMOS/LVTTL interface levels. Core supply pin. Differential output for the synthesizer. LVHSTL interface levels. Differential output for the synthesizer. LVHSTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register Pullup on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of Pullup S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Selects between XTAL input or test input as the PLL reference source. Selects XTAL input when HIGH. Selects TEST_CLK Pullup when LOW. LVCMOS/LVTTL interface levels. Pulldown Test clock input. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 4, 13, 30 2, 3 5, 6 7 8, 16 9 10, 26 11, 12 14, 15 Name VDDO FOUT2, nFOUT2 FOUT3, nFOUT3 OE GND TEST VDD FOUT4, nFOUT4 FOUT5, nFOUT5 MR
17
Input
18 19 20 21 22 23 24, 25 27 28, 29
S_CLOCK S_DATA S_LOAD VDDA XTAL_SEL TEST_CLK XTAL_OUT, XTAL_IN VCO_SEL
Input Input Input Power Input Input Input Input
FOUT0, Output Differential output for the synthesizer. LVHSTL interface levels. nFOUT0 FOUT1, 31, 32 Output Differential output for the synthesizer. LVHSTL interface levels. nFOUT1 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Outputs FOUT0:FOUT5 Disabled; LOW Disabled; LOW Enabled nFOUT0:nFOUT5 Disabled; HIGH Disabled; HIGH Enabled TEST_CLK
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs OE 0 0 1 XTAL_SEL 0 1 0 Selected Source XTAL_IN, XTAL_OUT TEST_CLK
1 1 XTAL_IN, XTAL_OUT Enabled Enabled After OE switches, the clock outputs are disabled or enabled following a rising and falling VCO edge as shown in Figure 2.
nVCO VCO
Disabled
Enabled
OE
nFOUT0:5 FOUT0:5
FIGURE 2. OE TIMING DIAGRAM
8427DY-02
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
256 M8 0 0 0 * 0 * 128 M7 0 0 0 * 1 * 64 M6 1 1 1 * 1 * 32 M5 1 1 1 * 0 * 16 M4 1 1 1 * 0 * 8 M3 1 1 1 * 0 * 4 M2 0 0 0 * 0 * 2 M1 0 0 1 * 0 * 1 M0 0 1 0 * 0 * 1 0
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
VCO Frequency (MHz) 249.99 252.08 254.17 * 400 * M Divide 120 121 122 * 192 *
497.91 239 0 1 1 1 0 1 1 1 500 240 0 1 1 1 1 0 0 0 NOTE 1: These M divide values and the resulting frequencies correspond to an input frequency of 16.6667MHz.
TABLE 3C. SERIAL MODE FUNCTION TABLE
Inputs MR H L L L L L S_LOAD S_CLOCK X L L L X X L L X S_DATA X X Data Data Data X Reset. Forces outputs Differential LOW. FOUTx = Low, nFOUTx = High. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. Conditions
L H Data NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3D. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
N2 0 0 0 0 1 1 1 1 Input N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divider Value 2 4 8 16 1 2 4 8 Output Frequency (MHz) Minimum Maximum 125 250 62.5 31.25 15.625 250 125 62.5 31.25 125 62.5 31.25 500 250 125 62.5
8427DY-02
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V 50mA 100mA 47.9C/W (0 lfpm) 34.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA for 32 Lead LQFP for 32 Lead VFQFN Storage Temperature, TSTG
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDD0 Parameter Core Supply Analog Voltage Ouput Voltage Power Supply Current Analog Supply Current Ouput Supply Current No Load Test Conditions Minimum 2.375 2.375 1.6 Typical 2.5 2.5 1.8 235 18 0 Maximum 2.625 2.625 2.0 Units V V V mA mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VIH VIL IIH Input High Voltage Input Low Voltage Input High Current MR, S_LOAD, TEST_CLK XTAL_SEL, VCO_SEL, S_CLOCK, S_DATA, OE MR, S_LOAD, TEST_CLK XTAL_SEL, VCO_SEL, S_CLOCK, S_DATA, OE VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V VDD = 2.625V, VIN = 0V -5 -150 1. 5 0.4 Parameter Test Conditions Minimum 1.7 -0.3 Typical Maximum VDD + 0.3 0.7 150 5 Units V V A A A A V V
IIL
Input Low Current
Output TEST; NOTE 1 High Voltage Output TEST; NOTE 1 VOL Low Voltage NOTE 1: Outputs terminated with 50 to VDDO/2. VOH
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Test Conditions Minimum 0.9 0 40 Typical Maximum 1.3 0.4 60 1. 1 Units V V % V
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VOH VOL VOX Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing 0.6 VSWING NOTE 1: Outputs terminated with 50 to GND. See 2.5V Output Load Test Circuit figure in the Parameter Measurement Information section. NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum 12 Typical Maximum 40 50 7 1 Units MHz pF mW Fundamental
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter TEST_CLK fIN Input Frequency XTAL; NOTE 1 Test Conditions VCO select = 1 VCO select = 0 (bypass mode) 12 Minimum 10 Typical Maximum 40 40 0 40 Units MHz MHz MHz
S_CLOCK 50 MHz NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz or 500MHz. Using the minimum frequency of 12MHz valid values of M are 167 M 333. Using the maximum frequency of 40MHz valid values of M are 50 M 100.
8427DY-02
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Test Conditions FOUT = 200 Minimum Typical Maximum 500 100 75 50 50 200 200 200 200 5 60 fOUT = 200MHz fOUT = 200MHz fOUT = 200MHz fOUT = 200MHz 20% to 80% 7 333 5 5 5 5 50 1 30 0.4 -40 10 667 33.33 0.6 FOUT = 267 FOUT = 333 FOUT = 400 FOUT = 200 FOUT = 267 FOUT = 333 FOUT = 400 Units MHz ps ps ps ps ps ps ps ps ps ps KHz % dB dB ps ns ns ns ns % ms
TABLE 7. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol FMAX Parameter Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter ; NOTE 1, 3
tjitt(T50)
50 Cycle Jitter
tjit(per) tsk(o)
FM FMF Refspur SSCred tR / tF tS tH odc tLOCK
Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 SSC Modulation Frequency; NOTE 4, 5 SSC Modulation Factor ; NOTE 4, 5 Reference Spur Spectral Reduction; NOTE 4, 5 Output Rise/Fall Time Setup Time Hold Time Output Duty Cycle PLL Lock Time S_DATA to S_CLOCK S_CLOCK to S_LOAD S_DATA to S_CLOCK S_CLOCK to S_LOAD
See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Spread Spectrum clocking enabled. NOTE 5: Using a 16.6667MHz quar tz cr ystal.
8427DY-02
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REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.5V5% 1.8V0.2V nFOUTx VDD, VDDA V DDO
Qx
SCOPE
FOUTx nFOUTy
LVHSTL
FOUTy GND
nQx
tsk(o)
0V
2.5V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nFOUT0:5 FOUT0:5
nFOUT0:5 FOUT0:5
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
dBm
Frequency
SPUR REDUCTION
8427DY-02
tcycle n+1
tcycle n
tcycle n + 50
tcycle n + 50 + 50
tjit (50) = tcycle n - tcycle n +50 5000 consective cycles 100 measurements
T50 CYCLE-TO-CYCLE JITTER
VOH
Reference Spur
VREF VOL
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
PERIOD JITTER
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ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
VOX 60% 50% 40%
nFOUT0:5 FOUT0:5
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT CROSSOVER VOLTAGE
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8427-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
2.5V VDD .01F VDDA .01F 10F 10
FIGURE 3. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8427-02 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 4 below were determined using a 16.66MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 4. CRYSTAL INPUt INTERFACE
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ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
The ICS8427-02 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 5B. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 5B. It is important to note the ICS8427-02 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction.
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 32.55kHz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 5A below. The ramp profile can be expressed as: * Fnom = Nominal Clock Frequency in Spread OFF mode (200MHz with 16.6667MHz IN) * Fm = Nominal Modulation Frequency = Reference Frequency 16 x 32 * = Modulation Factor (0.5% down spread) (1 - ) fnom + 2 fm x x fnom x t when 0 < t < 1 , 2 fm (1 - ) fnom - 2 fm x x fnom x t when 1 < t < 1 2 fm fm
Fnom
- 10 dBm
B
A
0.5/fm 1/fm
FIGURE 5A. TRIANGLE FREQUENCY MODULATION
FIGURE 5B. 200MHZ CLOCK OUTPUT
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(1 - ) Fnom
= .4%
IN
FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON
REV. D JUNE 28, 2005
PRELIMINARY
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ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
X1 C2
LAYOUT GUIDELINE
The schematic of the ICS8427-02 layout example used in this layout guideline is shown in Figure 6. This layout example is used as a general guideline. The layout in the actual system
C1
VDD=2.5V VDDO=1.8V
U1 VDDO = 1.8V 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25
C10 .1uF
C8 .1uF
nFOUT1 FOUT1 VDDO nFOUT0 FOUT0 VCO_SEL VDD XTAL1
VDD = 2.5V 24 23 22 21 20 19 18 17 R1 10
C7 .1uF
VDD0 = 1.8V
VDD0 = 1.8V
VDD = 2.5V
9 10 11 12 13 14 15 16
ICS8427-02
TEST VDD FOUT4 nFOUT4 VDDO FOUT5 nFOUT5 GND
C9 .1uF
VDDO FOUT2 nFOUT2 VDDO FOUT3 nFOUT3 OE GND
XTAL2 TEST CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR
TEST CLK XTAL_SEL S_LOAD S_DATA S_CLOCK
C3 0.01u
C4 10u
Zo = 50
Zo = 50 C5 .1u C6 .1uF
R2 50
R3 50
FIGURE 6. SCHEMATIC
OF
RECOMMENDED LAYOUT
8427DY-02
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Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8427-02. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8427-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 235mA = 616.9mW Power (outputs)MAX = 32.6mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 32.6mW = 195.6mW
Total Power_MAX (3.465V, with all outputs switching) = 616.9mW + 195.6mW = 812.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.813W * 42.1C/W = 104.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE JA
FOR
32-PIN LQFP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8C/W 55.9C/W 50.1C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9C/W 42.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. JAVS. AIR FLOW TABLE
FOR A
32 LEAD VFQFN
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
8427DY-02
200
TBD
500
TBD
REV. D JUNE 28, 2005
34.8C/W
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15
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 7.
VDDO
Q1
VOUT RL 50
FIGURE 7. LVHSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L DD_MAX
-V
OH_MIN
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DD_MAX
-V
OL_MAX
Pd_H = (0.9V/50) * (2V - 0.9V) = 19.8mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW
8427DY-02
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16
REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 9A. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9B. JAVS. AIR FLOW TABLE
FOR A
32 LEAD VFQFN
JA 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W
TRANSISTOR COUNT
The transistor count for ICS8427-02 is: 5084
8427DY-02
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17
REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc Reference Document: JEDEC Publication 95, MS-026
8427DY-02
MINIMUM
NOMINAL 32
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0 0.60 0.75 7 0.10 1.40 0.37 0.15 1.45 0.45 0.20
www.icst.com/products/hiperclocks.html
18
REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
32 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR A
TABLE 10B. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL N A A1 A3 b ND NE D D2 E E2 e L 0.30 1.25 1.25 5.00 BASIC 2.25 5.00 BASIC 2.25 0.50 BASIC 0.40 0.50 3.25 3.25 0.18 0.80 0 MINIMUM NOMINAL 32 --0.25 Ref. 0.25 0.30 8 8 1.00 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
8427DY-02
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19
REV. D JUNE 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8427-02
500MHZ, LOW JITTER LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
Marking ICS8427DY-02 ICS8427DY-02 ICS8427DK-02 ICS8427DK-02 Package 32 Lead LQFP 32 Lead LQFP 32 Lead VFQFN 32 Lead VFQFN Shipping Packaging tray 1000 tape & reel tray 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 11 ORDERING INFORMATION
Part/Order Number ICS8427DY-02 ICS8427DY-02 ICS8427DK-02 ICS8427DK-02T
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8427DY-02
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20
REV. D JUNE 28, 2005

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